The present invention relates to semiconductor devices and methods for driving the same. More particularly, the present invention relates to semiconductor devices which are applicable to neural network computers (neurocomputers), for example, and allows multilevel information to be stored therein, and also relates to methods for driving the devices.
As multimedia has been developed, semiconductor devices are more and more required to improve their performance. For example, to process a large capacity of digital information, even CPUs of personal computers operating at high speeds of 1 GHz or more have come onto the market.
To meet such a demand for improving the performance of semiconductor devices, semiconductor fabricators have improved the performance mainly with techniques of downsizing the semiconductor devices.
However, even physical limitations are now pointed out in downsizing the semiconductor devices, and therefore, improvement in the semiconductor devices by further downsizing is not expected in consideration of fabrication cost.
To solve this problem, in place of digital information processing techniques to date that perform computations using a binary signal of “1” or “0”, multilevel cell technologies for converting information into three or four levels, technologies for computers (neurocomputers) that perform computation by mimicking the behavior of the brain of an animal with the application of the multilevel cell technologies, and the like, have been researched.
The brain of an animal is basically composed of nerve cells, which are called neurons and have a computing function, and nerve fibers, each of which transmits a computing result of a neuron to another neuron, i.e., serves as so-called wiring.
A neurocomputer is composed of a large number of neuron units, which are made of semiconductor elements corresponding to neurons, and a large number of synapse units, which transmits signals to the neuron units and add weights to the signals. Combinations of the neuron units and the synapse units are hereinafter referred to as neuron elements.
When information signals having different “weights” and being output from a plurality of previous-stage neuron elements are input to a neuron element, the information signals are added to this neuron element. When the sum of the information signals exceeds a threshold value, the neuron element “fires” to allow a signal to be output to a subsequent-stage neuron element. Information is processed by repeating this operation.
A process by which the brain of an animal learns is considered a process of varying weights on synaptic connections. That is to say, the weights are gradually modified with respect to various input signals so as to obtain an appropriate output, and finally the weights stay at appropriate values.
To configure a neural network having such a leaning function, it is necessary to vary the strength on each synaptic connection as required and to store the varied strength. Therefore, the multilevel cell technologies have become essential for implementing neurocomputers.
The neurocomputer described above is an example of application of the multilevel cell technologies. Naturally, multilevel memories in which multilevel information is stored therein with stability have been researched actively. As is evident from these factors, the multilevel cell technologies for information have become extremely important for future semiconductor devices.
As an example of such multilevel cell technologies, a known technique for allowing information with at least three levels to be stored in a single memory cell was disclosed in Japanese Laid-Open Publication No. 8-124378.
FIG. 49 is a cross-sectional view showing a known semiconductor device functioning as a multilevel memory. As shown in FIG. 49, the known semiconductor device includes: a silicon substrate 1107; well lines BUL1 and BUL 2 buried in the silicon substrate 1107; PZT films 1109 made of a ferroelectric and formed on the well lines BUL1 and BUL 2, respectively; a word line WL1 formed on the PZT films 1109; a bit line BL1 formed over the word line WL1 and the well line BUL1; and a bit line BL2 formed over the word line WL1 and the well line BUL2. Although not shown, source and drain are provided in each of the well lines BUL1 and BUL2. The bit line BL1 is connected to the drain in the well line BUL1 via a bit contact (not shown), while the bit line BL2 is connected to the drain in the well line BUL2 via a bit contact.
Information is written by changing the polarization in the PZT film 1109 upon the application of a voltage to the word line WL1 and the well lines BUL1 and BUL2.
FIG. 50 is a graph showing a relationship between a voltage VGB applied to the gate electrode (=the potential at the gate electrode-the potential at the well) and the magnitude of the polarization of the ferroelectric (i.e., hysteresis characteristics) in each memory cell of the known device. Since the ferroelectric has hysteresis characteristics, the polarization state changes depending on the history of the applied voltage, and even after the voltage has been removed, the polarization state remains as indicated by a point A, B or C in FIG. 50. If a voltage V=V1, at which the ferroelectric is in a saturated polarization state is applied and then removed, the polarization is at the point A. When a voltage is removed after the application of a voltage V=−V2, the polarization is at the point C. If a voltage V=−V1 is applied and then removed, the polarization is at the point B.
FIG. 51 is a graph showing the relationship between a drain current I and a gate voltage VGB in a memory cell when the ferroelectric is in the state indicated by the point A, C or B in FIG. 50. In FIG. 51, the left-side curve, the middle curve and the right-side curve correspond to the states indicated by the points A, C and B, respectively. In the state indicated by the point A, the ferroelectric exhibits a large positive polarization, so that a threshold voltage VtA of the memory cell is lower than a threshold voltage VtC in the state indicated by the point C at which no polarization is exhibited. In the state indicated by the point B, the ferroelectric exhibits a large negative polarization, so that a threshold voltage VtB of the memory cell is higher than the threshold voltage VtC in the state indicated by the point C at which no polarization is exhibited. By thus providing the ferroelectric with the three polarization states indicated by the point A, C and B, the memory cell can be controlled to have three different levels of threshold voltages. Therefore, it is possible to store information with three levels in the memory cell corresponding to the values of these threshold voltages. The known technique described above indicates that if a polarization state between the points A and C is used, the number of levels can be further increased.
However, the known technique has a basic problem that the polarization state “C” is difficult to obtain accurately. Specifically, in the known technique, when a voltage is removed after the ferroelectric has exhibited a small polarization upon the application of an appropriate voltage, the polarization comes close to zero. However, as shown in FIG. 50, the hysteresis of the ferroelectric changes greatly in the vicinity of a coercive voltage Vc, while the absolute value of the voltage −V2 is essentially close to the coercive voltage Vc. Thus, the polarization of the ferroelectric is extremely difficult to control, resulting in that the polarization value after the removal of the voltage changes greatly only by a small variation in the voltage V2 caused by noise or the like. In addition to such a variation in the write voltage, variations in the crystal state and the thickness of the ferroelectric, for example, also vary the coercive voltage Vc. This results in difficulty in obtaining stable multilevel storage properties with high reliability and excellent reproducibility. The coercive voltage herein refers to a voltage required for changing the hysteresis of the ferroelectric largely to alter the distribution of the charge in a ferroelectric capacitor.